Data stored in a volatile memory device, such as a dynamic RAM (DRAM) and a static RAM (SRAM), is lost when the power is turned off, and data stored in a non-volatile memory device is maintained even though the power is turned off. While the volatile memory device can have the advantage of a high speed, the non-volatile memory device may operate at a relatively low speed.
An example of a flash memory device is discussed in U.S. Pat. No. 6,465,293 ('293). According to the '293 patent, a semiconductor substrate on which an isolation layer is formed is provided and an oxide layer is formed on the substrate and the isolation layer, and the oxide layer is patterned to expose a portion of the substrate on which a floating gate is to be formed to thereby form an oxide pattern. A tunnel oxide layer and a first polysilicon layer are sequentially formed on the substrate including the oxide pattern, and then the first polysilicon layer is removed and planarized until the tunnel oxide layer is exposed to thereby form a floating gate self-aligned by the oxide pattern through which the substrate is partially exposed.
The exposed tunnel oxide layer and the oxide pattern are sequentially etched to a predetermined depth, and a dielectric layer is coated on the substrate including the etched tunnel oxide layer and the etched oxide pattern. A second polysilicon layer, a tungsten silicide layer and a hard mask layer are sequentially formed on the substrate and are patterned to thereby form a control gate. Impurities are implanted onto the substrate at both sides of the floating gate to thereby form a junction area.
As the level of integration in semiconductor device increases an aspect ratio of an opening defined by the above oxide pattern may be increases so that voids may be formed in the first polysilicon layer formed in the opening due to a shape of the oxide pattern.
The void in the first polysilicon layer may be exposed by the planarization process, which may produce a seam on a surface of the floating gate. The seam on the surface of the floating gate may deteriorate the breakdown voltage of the dielectric layer on the floating gate, and may reduces the coupling ratio of the flash memory device. In addition, the seam on the surface of the floating gate may increase the leakage current through the dielectric layer.
It has been suggested that an upper portion of the first polysilicon layer may be removed and an additional polysilicon layer may be formed in place of the removed first polysilicon layer to remove the void in the first polysilicon layer. However, the etchant used to remove the first polysilicon layer may cause damage to the tunnel oxide layer between the first polysilicon layer and the substrate, which may deteriorate the breakdown voltage of the tunnel oxide layer.